Charge-coupled devices (CCD) image sensors are photosensitive devices which are frequently used in electronic imaging. As technology has advanced, the resolution of these CCD image sensors has increased and the number of image sensor sites has increased. These sensor sites are called pixels. A line at a time of information is read in parallel into a shift register. the information is sequentially read out of the shift register. A problem with this arrangement is that as the number of pixels increases, the time to read out the charge from all the pixels increases and hence the frame rate actually decreases. In order to maintain or increase the frame rate of an area image sensor, two approaches have been used. The first is simply to increase the horizontal shift register clock frequency to increase the readout rate and the second is to employ analog, multiple shift registers and readout information from each shift register through an output terminal to increase the frame rate without changing the horizontal clock frequency or both.
Normal video image sensors are designed for 30 frames per second. There are, however, situations where it is highly desirable to have an increasing rate of frames per second. In some specific scientific applications it is desirable to have at least 40,000 frames per second. Such type of arrangements require the use of the multiple readout shift registers. With large numbers of pixels and multiple outputs, it is important to analyze the output of a CCD image sensor 10 to determine whether there are defects in the image sensor pixels.
A real time display (image) on a monitor is needed for test and analysis. In the past, this has been accomplished using expensive frame stores. Turning now to FIG. 1, we see a CCD image sensor 10 with which the present invention can be used. To use a conventional display there can, for example, be 512 pixels per line and 512 lines. In FIG. 1, there are 64 shift registers 11, one for each block of image data. More particularly, there are 64 blocks of information in the CCD. Each shift register 11 corresponds to a single block of image data. Each output from one of the 64 analog shift registers 11 is coupled to a conventional sample and hold circuit 14.
Turning now to FIG. 2, sample and hold circuits 14 provide input into individual A/D converter 17. Accordingly, since there are 64 blocks, there are 64 sample and hold circuits and 64 A/D converters. Under the control of timing and control circuit 25 the sample and hold circuits 14 deliver analog data to A/D converters 17. The A/D converters deliver digital pixel data to storage locations in a frame store 16 under the control of microcomputer 22. The number of image locations in the frame store 16 will correspond to twice the total number of pixels in the CCD image sensor 10. For example, the first A/D converter 17 feeds a dual block (two frames) store 1. This corresponds to the traditional two frames required to display a complete image. The microcomputer 22 control all the necessary programming for providing timing and addressing information into the frame store 16 and to deliver each digitized pixel signal to its appropriate location in each dual block store in the frame store 16. It also controls the operation of the readout from the frame store 16 to a digital to analog converter 27 which applies its output to a display unit 26. A keyboard 28 associated with the microcomputer, permits a user to control the frame store in accordance with software programming for display on the CRT display unit (monitor) 27.
For a more complete disclosure of a system which uses a CCD with a plurality of blocks of information and control electronics see commonly assigned U.S. Pat. No. 4,638,371 to Milch the disclosure of which is incorporated by reference herein.
When it is desired to visually determine if there are defects in the CCD, then a predetermined target pattern is focused onto the CCD and repeatedly readout from the CCD into the frame store 16. Pixel information is then delivered into the display 26 for visual test and defect analysis. Such defects can be bright point defects and dim point defects. Using this arrangement as a test device requires expensive frame store arrangements as well as special programming.
For a CCD sensor with single output the image is normally displayed onto a NTSC display CRT or monitor or onto a high persistence display or monitor depending on the frame rate at which the sensor is operating. If the sensor operates at less than 10 frames per second then the flicker on the monitor becomes unacceptable. For such sensor testing the video signal from the sensor is sent to a frame store and refreshed onto the monitors at 60 frames per second. This means the picture on the monitor is updated at the frame rate of the sensor but displayed at 60 frames per second. This arrangement normally needs a frame store and an associated microcomputer as shown in FIG. 2. Now for a sensor with 64 outputs we need 64 frame stores each with its high speed A/D. The 64 frame stores need to be synchronized and coordinated by a computer. This requires the development of expensive necessary software. For testing the wafers and packaged devices this elaborate expensive arrangement will increase the cost of the device, but it should be recognized that all that is needed for the test purposes is to identify bright point defects and dim points, charge transfer inefficiencies and smear.